1. Field of the Invention
The present invention relates to a metal nitride oxide semiconductor (MNOS) type memory using a threshold voltage variation (.DELTA.Vth) due to charging of a single electron which occurs when the width of a channel of a memory is set to be smaller than or equal to the Debye screen length (LD) of an electron, and a driving method thereof.
2. Description of the Related Art
Non-volatile MNOS-type memories in the present invention indicate MNOS memories and metal oxide nitride oxide semiconductor (MONOS) memories.
FIG. 1A is a schematic cross-sectional view of an MNOS memory representative of conventional non-volatile memory. As shown in FIG. 1A, in the conventional MNOS memory, a source 12 and a drain 13, which are doped with n.sup.+, are formed on a p-type semiconductor substrate 10, having a channel 11 of an inversion layer therebetween. A tunnel oxide layer 14 composed of SiO.sub.2 and a thin nitride layer 15 composed of Si.sub.3 N.sub.4 are sequentially formed on the channel 11, and then a gate 16 is stacked on the resultant structure. Trap sites 17, which are charged with electrons, are formed between the tunnel oxide layer 14 and the thin nitride layer 15 stacked between the channel 11 and the gate 16.
The operation characteristics of a non-volatile MNOS memory having such a structure are shown as a current-voltage (I-V) characteristic curve in FIG. 1B. Here, a gate voltage capable of operating memory cells, that is, a threshold voltage, is higher by .DELTA.Vth when electrons are trapped than when no electrons are trapped. In other words, when trap sites are charged with electrons by Fowler-Nordheim tunneling (FNT) or channel hot electron injection (CHEI), the electrons do not leak even if power is turned off. Upon reading, the electrons charged in trap sites screen the channel, causing a variation in the threshold voltage. The charged state and the discharged state described above are designated as 1 and 0, respectively, and non-volatile MNOS memories store the information corresponding to 1 and 0.
Floating gate (FG)-type SET flash memories, which are existing memories using single electron charging, have been studied by many people. Hitachi introduced a 128 M SET flash memory which operates at room temperature (U.S. Pat. No. 5,600,163) early in 1998. IBM has U.S. Pat. Nos. 5,714,766 AND 5,801,401 wherein an enormous number of nano crystals are formed on an existing FET channel, and the resultant structure is applied as a floating gate. Fujitsu in Appl. Phys. Lett Vol 71, p 353, 1997, and Princeton University in Science, Vol 275, p 649, 1997 introduced a non-volatile memory which operates at room temperature using the principle that a single electron can screen a channel by setting the size of a floating gate on an FET to be several nanometers and setting the width of a channel to be smaller than the Debye screen length of an electron. NEC in Appl.Phys.Lett Vol 71, p 2038, 1997, and NTT in Electron.Lett, Vol 34, p 45, 1998 introduced a memory which operates a single electron transistor as an electrometer which indirectly detects the presence of electrons to a precision of a single electron and thus determines whether electrons are stored in a floating gate. However, the SET flash memory of Hitachi has critical drawbacks in that the operating voltage is very high, and nano crystals used for a floating gate and nano crystals applied as a channel cannot be arbitrarily controlled in contrast to other memories. The memory introduced by IBM causes fluctuations in .DELTA.Vth and temperature due to the difficulty in maintaining the sizes of nano crystals, which are applied as a floating gate, to be uniform. The memories introduced by Fujitsu and Princeton University have problems in that it is difficult to commercialize the memories as non-volatile memories since the retention time is only several seconds, and particularly, reproducible and uniform control of a floating gate to have a size of several nanometers cannot be secured. In the memories produced by NEC and NTT, the structure of elements and a fabrication process thereof are very complicated. According to the results of analysis made on the characteristics and realizability of the memory devices proposed up until now, a method of forming a floating gate of numerous nano crystals, which is proposed by IBM, that is, constitution of one bit using more than several tens of electrons, was estimated to provide excellent reliability. Therefore, non-volatile memories which are not limited in size, apply the single electron charging phenomenon, and can operate at a low voltage, are required.